Such circuits may for example be circuits that repeat with a preset and constant pitch, such as the circuits that are used in memory devices, for example in row and/or column decoders, and especially memory devices associating, in a given memory cell, an SRAM (static random access memory) elementary memory cell and one or more, for example two or four, nonvolatile elementary memory cells, in particular double-gate EEPROM (electrically-erasable and programmable read-only memory) elementary memory cells.
Furthermore, for example, MOS transistors placed near one another may also be found in the inverters of SRAM elementary memory cells.
The distance between two neighboring MOS transistors is often constrained by lithography constraints that specify minimum distances between the two gate regions or even between the channels of the two transistors.
These drawbacks are also encountered when fabricating transistors in double gate level technologies, such as the technologies found in memory devices associating, in a given memory cell, an SRAM elementary cell and one or more nonvolatile elementary memory cells, for example double-gate EEPROM memory cells.
SRAM elementary memory cells are volatile memory cells, i.e., the data they store is lost if their power supply is cut but they may be accessed very rapidly and have an infinite cycling endurance.
Nonvolatile elementary memory cells, for example EEPROM memory cells, allow data to be preserved in the event of a power cut but cannot be cycled indefinitely.
A memory cell associating an SRAM elementary cell and one or more (for example, two or four) nonvolatile cells makes it possible to combine the advantages of the two approaches, namely the speed and the infinite endurance of the SRAM memory and the nonvolatility of the nonvolatile memory, flash or EEPROM memory for example.
Under normal operating conditions, data is written and read in such memory cells to/from the SRAM elementary cell. On the other hand, especially when power is cut, the content of the SRAM elementary cell is transferred to the nonvolatile elementary memory cell(s) that are associated therewith.
Then, especially when power returns, the data contained in the nonvolatile memory cells are reloaded into the corresponding SRAM elementary memory cell.
Examples of architectures of such memory cells associating SRAM memory and nonvolatile memory are described in the documents U.S. Pat. No. 4,132,905, U.S. Pat. No. 4,467,451, U.S. Pat. No. 4,980,859, U.S. Pat. No. 7,164,608 and U.S. Pat. No. 8,018,768 and in the French patent applications filed under the numbers 1355439 (corresponding to US 2014/0369120), 1355440 (corresponding to US 2014/0369119) and 1356720 (corresponding to US 2015/0016188).
When the one or more transistors of the nonvolatile elementary memory cell are one or more floating-gate transistors that thus comprise two polysilicon levels per example, all the transistors of the SRAM cell are advantageously produced in these two polysilicon levels.
Then, as regards the transistors of the SRAM cell, a short-circuit is then formed between the two polysilicon layers either via an electrical contact or by bringing them into physical contact by removing the gate dielectric located between the two polysilicon layers.
In conventional etching operations, the ends of the effective gates of the transistors, i.e., the gates formed in the first polysilicon layer, are rounded, thereby requiring the size of these gate regions to be increased in order to prevent these rounded portions from getting too close to the channel region, which could lead to leakage. Moreover, the definition of the geometry of the gate region gets worse as the thickness of the polysilicon stack to be etched increases. These defects are sometimes corrected by optical proximity corrections (OPCs) but in fine they generally do not allow structures to be obtained the gate regions of which have satisfactorily square edges.